From: kfraser@localhost.localdomain <kfraser@localhost.localdomain>
Date: Thu, 30 Aug 2007 17:53:54 +0000 (+0100)
Subject: Support extensions to Intel architecture for TXT/SMX.
X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~14987^2~36
X-Git-Url: https://dgit.raspbian.org/%22http:/www.example.com/cgi/%22https:/%22bookmarks:///%22http:/www.example.com/cgi/%22https:/%22bookmarks:/?a=commitdiff_plain;h=527571ecefe60c8800cee21823917d3aa8cbfca1;p=xen.git

Support extensions to Intel architecture for TXT/SMX.
Signed-off-by: Joseph Cihula <joseph.cihula@intel.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
---

diff --git a/xen/arch/x86/domain_build.c b/xen/arch/x86/domain_build.c
index a7927c6f63..c8deceef83 100644
--- a/xen/arch/x86/domain_build.c
+++ b/xen/arch/x86/domain_build.c
@@ -26,6 +26,7 @@
 #include <asm/desc.h>
 #include <asm/i387.h>
 #include <asm/paging.h>
+#include <asm/e820.h>
 
 #include <public/version.h>
 #include <public/libelf.h>
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 0795420820..163cc7752e 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -262,17 +262,19 @@ int vmx_cpu_up(void)
 
     if ( eax & IA32_FEATURE_CONTROL_MSR_LOCK )
     {
-        if ( !(eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) )
+        if ( !(eax & (IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX |
+                      IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX)) )
         {
-            printk("CPU%d: VMX disabled\n", cpu);
+            printk("CPU%d: VMX disabled by BIOS.\n", cpu);
             return 0;
         }
     }
     else
     {
-        wrmsr(IA32_FEATURE_CONTROL_MSR,
-              IA32_FEATURE_CONTROL_MSR_LOCK |
-              IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0);
+        eax = (IA32_FEATURE_CONTROL_MSR_LOCK |
+               IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX |
+               IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX);
+        wrmsr(IA32_FEATURE_CONTROL_MSR, eax, 0);
     }
 
     vmx_init_vmcs_config();
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 22a72f4bd8..9504ea040d 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -77,6 +77,7 @@
 #define X86_FEATURE_MWAIT	(4*32+ 3) /* Monitor/Mwait support */
 #define X86_FEATURE_DSCPL	(4*32+ 4) /* CPL Qualified Debug Store */
 #define X86_FEATURE_VMXE	(4*32+ 5) /* Virtual Machine Extensions */
+#define X86_FEATURE_SMXE	(4*32+ 6) /* Safer Mode Extensions */
 #define X86_FEATURE_EST		(4*32+ 7) /* Enhanced SpeedStep */
 #define X86_FEATURE_TM2		(4*32+ 8) /* Thermal Monitor 2 */
 #define X86_FEATURE_CID		(4*32+10) /* Context ID */
diff --git a/xen/include/asm-x86/msr.h b/xen/include/asm-x86/msr.h
index 1f89ee0a37..1e24537566 100644
--- a/xen/include/asm-x86/msr.h
+++ b/xen/include/asm-x86/msr.h
@@ -122,8 +122,11 @@ static inline void wrmsrl(unsigned int msr, __u64 val)
 #define MSR_IA32_VMX_CR4_FIXED1                 0x489
 #define MSR_IA32_VMX_PROCBASED_CTLS2            0x48b
 #define IA32_FEATURE_CONTROL_MSR                0x3a
-#define IA32_FEATURE_CONTROL_MSR_LOCK           0x1
-#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON   0x4
+#define IA32_FEATURE_CONTROL_MSR_LOCK                     0x0001
+#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX  0x0002
+#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX 0x0004
+#define IA32_FEATURE_CONTROL_MSR_SENTER_PARAM_CTL         0x7f00
+#define IA32_FEATURE_CONTROL_MSR_ENABLE_SENTER            0x8000
 
 /* AMD/K8 specific MSRs */ 
 #define MSR_EFER 0xc0000080		/* extended feature register */
diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h
index 15bac913ae..f3eb48fb8c 100644
--- a/xen/include/asm-x86/processor.h
+++ b/xen/include/asm-x86/processor.h
@@ -80,6 +80,7 @@
 #define X86_CR4_OSFXSR		0x0200	/* enable fast FPU save and restore */
 #define X86_CR4_OSXMMEXCPT	0x0400	/* enable unmasked SSE exceptions */
 #define X86_CR4_VMXE		0x2000  /* enable VMX */
+#define X86_CR4_SMXE		0x4000  /* enable SMX */
 
 /*
  * Trap/fault mnemonics.